Japanese Unexamined Patent Publication No. 2009-290095 (Patent Literature 1) discloses a technique in which a diode element and a resistive element are arranged in parallel within a drain diffusion layer electrode in a planar logic circuit MOSFET (metal oxide semiconductor field effect transistor) used for a large-scale integrated circuit. With this technique, even if a voltage is low, a high performance transistor indicative of a precipitous change in a drain current to a gate voltage change can be realized.